1. Field of the Invention
This invention relates to a MIS (Metal Insulator Semiconductor) transistor type nonvolatile semiconductor memory device having a two-layer electrode structure made up of a floating gate and a control gate. In particular, the invention can be preferably realized as a MOS (Metal Oxide Semiconductor) transistor type nonvolatile semiconductor memory device.
2. Description of Related Art
In nonvolatile semiconductor memory devices such as EEPROMs and flash memories, high-concentration P-type regions called P-pockets are formed around electric-field moderating layers and the source and the drain to increase writing speed by increasing the efficiency of formation of hot carriers during writing operation.
A conventional nonvolatile semiconductor memory device is manufactured by the steps illustrated in FIGS. 12A through 12D. Specifically, a floating gate 3 is formed on a P-well region 1 formed in a substrate, with a first gate insulating film 2 therebetween. Then, a control gate 5 is formed on the floating gate 3, with a second gate insulting film 4 therebetween. After that, an oxide film 6 is formed to a suitable thickness and N-type impurity is ion-implanted to form a source 6a and a drain 6b, as shown in FIG. 12B. Also, an N-type impurity is diagonally ion-implanted to form electric-field moderating layers 7, as shown in FIG. 12C. Next, boron is diagonally ion-implanted and high-concentration P-type regions 8a, 8b called P-pockets are formed around the electric-field moderating layers 7 and next to the lower parts of the source 6a and the drain 6b, as shown in FIG. 12D.
However, when a nonvolatile semiconductor memory device is manufactured in the way described above, the high-concentration P-type region 8b is formed in contact with the bottom surface of the electric-field moderating layer 7 and the lower part of the drain 6b. As a result, the width of a depletion layer formed between the N-type regions of the electric-field moderating layer 7 and the drain 6b and the high-concentration P-type region 8b becomes narrow and the diffusion capacitance of this P-N junction increases. This increase in capacitance lengthens the time required for charging and discharging of charges, and consequently the switching speed of when reading operation of the semiconductor memory device is carried out is made slow.
It is therefore a first object of the invention to provide a semiconductor memory device and a method for manufacturing the same with which it is possible to suppress a delay in switching speed while quickening writing speed by eliminating the influence of a high-concentration region of the opposite conductive type formed adjacent to the bottom surface of an electric-field moderating layer and lower parts of source and drain layers.
One example of known nonvolatile memories in which electrical overwriting and erasing are possible is a flash memory. Generally, as shown in FIG. 18, a flash memory 100 consists of a large number of bits arrayed in a matrix. When reading and writing operations are carried out in this kind of flash memory 100, a voltage acts on the terminals of bits other than the selected bit (hereinafter referred to as non-selected bits) as well on the selected bit. Consequently, it sometimes happens that in non-selected bits charge is exchanged between the charge holding part of the bit and the terminal on which the voltage acts and data that had been held in the bit is lost as a result.
This phenomenon is called disturbance in a nonvolatile memory. A particular type of this disturbance is drain disturbance, which occurs when a voltage acts on the drain. Because the drain side edge of the gate electrode is square, a field concentration arises at this edge, and drain disturbance is sometimes caused with this as the reason.
To avoid this, as disclosed in Japanese Patent Application Laid-Open No. H. 5-299662 and Japanese Patent Application Laid-Open No. H. 6-237004, methods for suppressing drain disturbance by rounding off the drain side edge of a floating gate constituting the charge holding part so that a field concentration does not arise there are known. In the method disclosed in Japanese Patent Application No. H. 6-237004, a first insulating film, a polysilicon layer, a second insulating film and another polysilicon layer are formed and then anisotropic dry etching is carried out vertically as far as midway through the first insulating film. The etched side wall parts are then covered with a protecting film and isotropic etching is carried out to round both of the bottom edges of the floating gate. In the method disclosed in Japanese Patent Application Laid-Open No. H. 5-299662, a first insulating film, a polysilicon layer, a second insulating film and another polysilicon layer formed successively are anisotropically dry-etched vertically to form a gate oxide film, a floating gate, another gate oxide film and a control gate are formed. Then, with a source side region masked, the gate oxide film on the drain side is isotropically etched and the floating gate edge on the drain side is thereby exposed. After that, rounding of the drain side edge of the floating gate is carried out by thermal oxidation.
However, in these methods, the process of rounding the drain side edge of the floating gate carried out to suppress drain disturbance necessitates etching steps of anisotropic dry etching and isotropic etching.
It is therefore a second object of the invention to provide a manufacturing method by which it is possible to fabricate a two-layer gate type semiconductor memory device with which drain disturbance can be suppressed without isotropically etching the gate oxide film on the drain side.